The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). The ICs are usually formed using both P-channel and N-channel FETs in which case the IC is referred to as a complementary MOS or CMOS IC. There is a continuing trend to incorporate more circuitry having greater complexity on a single IC chip. To continue this trend, the size of each individual device in the circuit and the spacing between device elements, or the pitch, is reduced for each new technology generation.
As critical dimensions shrink, device components such as the gate length and the thickness of gate insulator layers are scaled down in substantial proportion with each generation. For the 65 nm technology generation, conventional gate insulator materials such as, for example, thermally grown silicon dioxide (SiO2) or deposited silicon oxynitride (SiON), when used alone, begin to exhibit excessive leakage current and thus provide only marginally sufficient electrical isolation between the gate electrode and the underlying channel of a transistor. Therefore, alternative materials having dielectric constants greater than about 7 (referred to herein as high-k dielectrics) have been considered for use with advanced devices including advanced CMOS devices. Gate insulators made from high-k dielectrics can be made thicker than those made with SiO2 or SiON without sacrificing capacitance, and thus offer the benefit of a significant reduction in leakage current. Candidate materials include transitional metal oxides, silicates, and oxynitrides such as hafnium oxides, hafnium silicates, and hafnium oxynitrides.
However, combining high-k dielectric insulators with traditional polycrystalline silicon gate electrodes often results in transistors having a higher than optimal threshold voltage (Vt), and channel mobility and drive current that are undesirably low for advanced devices including those of the 45 nm generation. Investigators have proposed that the resulting high Vt is related to defects at the high-k/polycrystalline silicon interface. Further, it has been proposed that the reduction in channel mobility is primarily the result of surface phonon scattering in high-k dielectric materials. To overcome this incompatibility, gate electrode layers fabricated from such metals as titanium nitride (TiN) have been inserted between high-k insulators and polycrystalline silicon electrodes in the gate stacks of high performance transistors. Such metal gates are effective in mitigating phonon scattering caused by high-k dielectrics in the channel region resulting in improved drive current. Metal gates thereby overcome the problems associated with high-k dielectrics used as gate insulators and thus enable further scalability to smaller critical dimensions by utilizing the inherently superior insulation these materials provide.
The effort to optimize the performance of polycrystalline silicon/metal composite gate electrode devices has led to an investigation into the composition and associated work function of the metallic component of such gate electrodes. For example, it has been demonstrated that using a metal gate having an optimized composition and work function can result in a transistor that operates at or near a desired Vt. Further, when metal layers are added to polycrystalline silicon electrodes, device performance characteristics such as channel drive current are improved because of the low resistance of such gates when operating in a direct current (DC) mode. However, when operating in an alternating current (AC) mode, the AC gate impedance of such devices has been shown to be unacceptably high. It has been proposed that high gate impedance may be the result of defects within the gate electrode at the metal/polycrystalline silicon interface. High AC gate impedance can adversely affect device performance by degrading the switching speed, and thus the frequency at which a transistor device may be operated.
Accordingly, it is desirable to provide semiconductor devices having doped silicon-comprising capping layers interposed between metal and polycrystalline silicon layers of a composite gate electrode to reduce the AC impedance of such gates. Further it is also desirable to provide methods for fabricating such semiconductor devices. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.